Steve Keckler - The University of Texas
While substantial research in NoCs have focused on interconnects for chip-multiprocessors, network technology also provides opportunities for scalable processor and memory system architectures. Microarchitectural networks, or micronets, are lightweight networks that are integrated tightly into a processor core, replacing common control and data busses. In this talk, I will describe the micronetworks that we designed and implemented in the TRIPS processor, a 130nm ASIC that is constructed from distributed and replicated processor elements (tiles). In particular, I will discuss the operand network used for data communication in the TRIPS core and how we were able to exploit the specific requirements of the processor execution model to implement single-cycle per hop operand delivery across a 5x5 array of execution, register, and data cache tiles. I will also describe the distributed processor protocols enabled by both data and control micronetworks and reflect on our experience of building a micronetwork-based processor.Steve Keckler - The University of Texas
While substantial research in NoCs have focused on interconnects for chip-multiprocessors, networ...all »Steve Keckler - The University of Texas
While substantial research in NoCs have focused on interconnects for chip-multiprocessors, network technology also provides opportunities for scalable processor and memory system architectures. Microarchitectural networks, or micronets, are lightweight networks that are integrated tightly into a processor core, replacing common control and data busses. In this talk, I will describe the micronetworks that we designed and implemented in the TRIPS processor, a 130nm ASIC that is constructed from distributed and replicated processor elements (tiles). In particular, I will discuss the operand network used for data communication in the TRIPS core and how we were able to exploit the specific requirements of the processor execution model to implement single-cycle per hop operand delivery across a 5x5 array of execution, register, and data cache tiles. I will also describe the distributed processor protocols enabled by both data and control micronetworks and reflect on our experience of building a micronetwork-based processor.«
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