OCIN06: Exploring NoC Design Space for Multicore Architectures
28:22
-
3 years ago
Chita Das - Penn State
Integration of multiple cores on the same chip has signaled the beginning of communication-centric, rather than computation-centric systems. Further, technology trends have accentuated the importance of interconnect-conscious design as global wire delays do not scale down as fast as gate delays in new technologies. Consequently, on-chip interconnects, also known as Network-on-Chip (NoC) architectures, are predicted to be a major bottleneck in designing embedded System-on-Chip (SoC) architectures and high-performance multicore architectures alike. However, unlike the traditional multiprocessor interconnects, design of scalable and high performance NoCs poses a whole set of new challenges in terms of on-chip area budget, energy/thermal efficiency, and reliability constraints. In this talk, we will summarize our research effort in designing NoC architectures encompassing performance, scalability, power, thermal and reliability issues. In particular, we will discuss the design of two novel router architectures, a dynamic buffer management scheme, and a 3D router architecture. The talk will conclude with pointers to our ongoing/futureChita Das - Penn State
Integration of multiple cores on the same chip has signaled the beginning of communication-centric, rather than co...all »Chita Das - Penn State
Integration of multiple cores on the same chip has signaled the beginning of communication-centric, rather than computation-centric systems. Further, technology trends have accentuated the importance of interconnect-conscious design as global wire delays do not scale down as fast as gate delays in new technologies. Consequently, on-chip interconnects, also known as Network-on-Chip (NoC) architectures, are predicted to be a major bottleneck in designing embedded System-on-Chip (SoC) architectures and high-performance multicore architectures alike. However, unlike the traditional multiprocessor interconnects, design of scalable and high performance NoCs poses a whole set of new challenges in terms of on-chip area budget, energy/thermal efficiency, and reliability constraints. In this talk, we will summarize our research effort in designing NoC architectures encompassing performance, scalability, power, thermal and reliability issues. In particular, we will discuss the design of two novel router architectures, a dynamic buffer management scheme, and a 3D router architecture. The talk will conclude with pointers to our ongoing/future«
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