OCIN06: Design Automation for Networks-on-chip: Status and Outlook
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2 years ago
Luca Benini, DEIS Universitá di Bologna
Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) platforms for high-end embedded applications. The heterogeneous nature of on-chip cores, and the energy efficiency requirements typical of embedded computing call for application-specific NoCs which eliminate much of the overheads connected with general-purpose communication architectures. However, application-specific NoCs must be supported by adequate design flows to reduce design time and effort.
We survey the main challenges in application-specific NoC design, and we outline a complete NoC design flow. Experimental results demonstrate that it is indeed possible to generate an application-specific NoC from a high-level specification in a few hours. Comparison with hand-tuned solutions shows that the automatically generated ones are very competitive from the area, performance and power viewpoint. Even though early results are promising, much work is still needed to develop NoC design flows that can handle the design implementation challenges posed by nanometer CMOS technology.Luca Benini, DEIS Universitá di Bologna
Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands ...all »Luca Benini, DEIS Universitá di Bologna
Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) platforms for high-end embedded applications. The heterogeneous nature of on-chip cores, and the energy efficiency requirements typical of embedded computing call for application-specific NoCs which eliminate much of the overheads connected with general-purpose communication architectures. However, application-specific NoCs must be supported by adequate design flows to reduce design time and effort.
We survey the main challenges in application-specific NoC design, and we outline a complete NoC design flow. Experimental results demonstrate that it is indeed possible to generate an application-specific NoC from a high-level specification in a few hours. Comparison with hand-tuned solutions shows that the automatically generated ones are very competitive from the area, performance and power viewpoint. Even though early results are promising, much work is still needed to develop NoC design flows that can handle the design implementation challenges posed by nanometer CMOS technology.«
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