OCIN06: Towards Light-Weight Intra-CMP Network Interfaces
32:44
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3 years ago
Manolis Katevenis, University of Crete
This talk will present opinions on future Network Interfaces (NI) for high-speed communication, and our research plans in this area. Processor-to-Network Interfaces (NI) are the next-to-be-removed system bottleneck. Challenges include low latency, high throughput even for small messages, high flexibility, and low cost. In chip multiprocessors (CMP's), the NI's between processor cores and the network-on-chip (NoC) must be small when compared to the processor itself and the local memory that it connects to (e.g. L1 cache). Consequently, (a) the NI must not require dedicated memory of its own, but rather it must dynamically share a portion of local memory; and (b) sending/receiving information (enqueue/dequeue/RDMA) must be as fast as reading/writing a few words in L1 cache.
A powerful and simplifying architecture is to combine and integrate the network interface into/with the cache controller. Send/enqueue resembles cache block flush/replace, or write-update protocols, or writing into non-cacheable address space with write-combine. Receive/dequeue resembles/benefits from cache block prefetching. Support for synchronization primitives can be provided by enqueue/dequeue operations optionally triggering new events or packet generation; these resemble cache coherence protocol actions.Manolis Katevenis, University of Crete
This talk will present opinions on future Network Interfaces (NI) for high-speed communication, an...all »Manolis Katevenis, University of Crete
This talk will present opinions on future Network Interfaces (NI) for high-speed communication, and our research plans in this area. Processor-to-Network Interfaces (NI) are the next-to-be-removed system bottleneck. Challenges include low latency, high throughput even for small messages, high flexibility, and low cost. In chip multiprocessors (CMP's), the NI's between processor cores and the network-on-chip (NoC) must be small when compared to the processor itself and the local memory that it connects to (e.g. L1 cache). Consequently, (a) the NI must not require dedicated memory of its own, but rather it must dynamically share a portion of local memory; and (b) sending/receiving information (enqueue/dequeue/RDMA) must be as fast as reading/writing a few words in L1 cache.
A powerful and simplifying architecture is to combine and integrate the network interface into/with the cache controller. Send/enqueue resembles cache block flush/replace, or write-update protocols, or writing into non-cacheable address space with write-combine. Receive/dequeue resembles/benefits from cache block prefetching. Support for synchronization primitives can be provided by enqueue/dequeue operations optionally triggering new events or packet generation; these resemble cache coherence protocol actions.«
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