OCIN06: On-Die Interconnects for Next Generation CMPs - Partha Kundu, Intel
32:05
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3 years ago
With ever-increasing transistors enabled by silicon technology, many computationally intensive problems are within reach of a single chip or small form-factor platforms. One such problem relates to solving the current data explosion problem for end-users. Single chip multi-processors (CMPs) in future will enable algorithms that in real-time aid in a) recognition of multi-modal objects, b) classification and categorization of unstructured data, and c) synthesis of complex physical objects as replicas of their actual counterparts. We examine commonly used kernels in such applications to understand the on-die interconnect's requirements for future CMPs. We find that many of these applications, although constrained by off-die bandwidth, can benefit from good caching solutions. We observe that a high performance on-die interconnect plays a key role in architecting such caching solutions.
Using an example 2D-mesh network topology, the talk discusses the design issues encountered in architecting such an interconnect. While previous research related to improving network throughput—specifically switch allocation, buffer management and flow control—may be leveraged and adapted effectively for on-die networks, we conclude that the significant challenge is one of managing power and improving the overall energy efficiency of the network.With ever-increasing transistors enabled by silicon technology, many computationally intensive problems are within reach of a single chip or...all »With ever-increasing transistors enabled by silicon technology, many computationally intensive problems are within reach of a single chip or small form-factor platforms. One such problem relates to solving the current data explosion problem for end-users. Single chip multi-processors (CMPs) in future will enable algorithms that in real-time aid in a) recognition of multi-modal objects, b) classification and categorization of unstructured data, and c) synthesis of complex physical objects as replicas of their actual counterparts. We examine commonly used kernels in such applications to understand the on-die interconnect's requirements for future CMPs. We find that many of these applications, although constrained by off-die bandwidth, can benefit from good caching solutions. We observe that a high performance on-die interconnect plays a key role in architecting such caching solutions.
Using an example 2D-mesh network topology, the talk discusses the design issues encountered in architecting such an interconnect. While previous research related to improving network throughput—specifically switch allocation, buffer management and flow control—may be leveraged and adapted effectively for on-die networks, we conclude that the significant challenge is one of managing power and improving the overall energy efficiency of the network.«
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