OCIN06:Interconnection Technologies for Large-Scale Multiprocessors - Ron Ho,Sun
25:37
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2 years ago
Continued scaling of silicon technologies has enabled single-die multiprocessors of moderate complexity, with chips integrating eight cores commercially available today. Pushing further to tens of cores requires either growing die sizes beyond acceptable cost and yield limits, or using multiple chips and connecting them with power-hungry and bandwidth-limited links. This talk will discuss two interconnect technologies for multi-core systems that enable integration of hundreds of cores. Proximity IO uses chip-to-chip capacitive coupling to give a grid of multiple chips the same bandwidth, latency, and power characteristics as if they were a single, larger, virtual die. To reduce the energy costs of on-chip communication, we also use on-chip capacitive coupling to drive data on low-swing wires across chips. Together, these technologies enable system exploration of a wide variety of interconnected computers. I will describe both technologies, show results of Silicon testchip, and discuss their limitations.
Continued scaling of silicon technologies has enabled single-die multiprocessors of moderate complexity, with chips integrating eight cores ...all »Continued scaling of silicon technologies has enabled single-die multiprocessors of moderate complexity, with chips integrating eight cores commercially available today. Pushing further to tens of cores requires either growing die sizes beyond acceptable cost and yield limits, or using multiple chips and connecting them with power-hungry and bandwidth-limited links. This talk will discuss two interconnect technologies for multi-core systems that enable integration of hundreds of cores. Proximity IO uses chip-to-chip capacitive coupling to give a grid of multiple chips the same bandwidth, latency, and power characteristics as if they were a single, larger, virtual die. To reduce the energy costs of on-chip communication, we also use on-chip capacitive coupling to drive data on low-swing wires across chips. Together, these technologies enable system exploration of a wide variety of interconnected computers. I will describe both technologies, show results of Silicon testchip, and discuss their limitations.
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