OCIN06: Scalar Operand Networks for Tiled Microprocessors - Michael Taylor, UCSD
40:52
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3 years ago
Scalar Operand Networks ("SONs") are a class of network optimized for the transport of operands among remote ALUs and memories. These sub-nanosecond networks, the central communication mechanism inside microprocessors, are perhaps the fastest class of network currently known to man, and are the lowest-latency apparatus for executing programs that have parallelism but are dependence-heavy.
This talk examines how scalable forms of SONs can allow microprocessors to scale to 100s or 1000s of functional units. The key is to organize chip resources as an array of small tiles, which are interconnected by a scalable, point-to-point, pipelined SON. This allows the frequency of these systems ("tiled microprocessors") to remain high, while the quantity of exposed on-chip resources (e.g., ALUs) remains linear with die area. Scalable SONs offer extremely low latency and occupancy communication, on the order of a few cycles, versus thirty or so for conventional multicore processors. This low cost expands the set of applications that can be parallelized and enables compilers to exploit fine-grained parallelism. This talk discusses the scalable SON we designed for the 16-issue MIT Raw 180 nm VLSI prototype, and some of the efforts we have made to characterize SON properties in general.Scalar Operand Networks ("SONs") are a class of network optimized for the transport of operands among remote ALUs and memories. These sub-na...all »Scalar Operand Networks ("SONs") are a class of network optimized for the transport of operands among remote ALUs and memories. These sub-nanosecond networks, the central communication mechanism inside microprocessors, are perhaps the fastest class of network currently known to man, and are the lowest-latency apparatus for executing programs that have parallelism but are dependence-heavy.
This talk examines how scalable forms of SONs can allow microprocessors to scale to 100s or 1000s of functional units. The key is to organize chip resources as an array of small tiles, which are interconnected by a scalable, point-to-point, pipelined SON. This allows the frequency of these systems ("tiled microprocessors") to remain high, while the quantity of exposed on-chip resources (e.g., ALUs) remains linear with die area. Scalable SONs offer extremely low latency and occupancy communication, on the order of a few cycles, versus thirty or so for conventional multicore processors. This low cost expands the set of applications that can be parallelized and enables compilers to exploit fine-grained parallelism. This talk discusses the scalable SON we designed for the 16-issue MIT Raw 180 nm VLSI prototype, and some of the efforts we have made to characterize SON properties in general.«
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